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Integrated Circuit Systems, Inc.
ICS9248-134
Frequency Timing Generator for PENTIUM II/III Systems
Recommended Application: For Intel Camino Style Chipsets Output Features: * 3 - CPUs @ 2.5V, up to 180MHz. * 1 - CPU/2 @ 2.5V. * 3 - IOAPIC @ 2.5V, PCI or PCI/2 * 3 - 3V66MHz @ 3.3V. * 11 - PCIs @ 3.3V * 1 - 48MHz, @ 3.3V fixed * 1 - 24/48MHz, @ 3.3V Features: * Support power management: Power down Mode from I2C programming. * * Spread spectrum for EMI control 0.25% center spread). Uses external 14.318MHz crystal
Pin Configuration
GND REF0 *SEL24_48#/REF1 VDDREF X1 X2 GND *FS0/PCICLK_F *FS1/PCICLK0 VDDPCI *FS2/PCICLK1 *FS3/PCICLK2 GND PCICLK3 PCICLK4 VDDPCI PCICLK5 PCICLK6 GND PCICLK7 PCICLK8 PCICLK9 VDDPCI PD# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDDL IOAPIC0 IOAPIC1 GND IOAPIC2 VDDL CPU/2 GND CPUCLK0 VDDL CPUCLK1 CPUCLK2 GND VDD66 3V66_0 3V66_1 3V66_2 GND66 SDATA SCLK VDD48 48MHz/FS4* 24_48MHz GND48
48-pin SSOP
*120K ohm pull-up to VDD on indicated inputs.
Key Specifications: * CPU Output Jitter: <250ps * * IOAPIC Output Jitter: <500ps 48MHz, 3V66, PCI Output Jitter: <500ps)
Functionality
FS4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FS3 FS2 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU 103.00 105.00 100.45 100.90 107.10 109.00 112.00 114.00 116.00 118.00 133.30 120.00 122.00 125.00 128.21 130.00 132.00 133.90 138.00 142.00 146.00 150.00 153.00 156.00 159.00 162.00 165.00 168.00 171.00 174.00 177.00 180.00 PCI 3V 66 34.33 68.67 35.00 70.00 33.483 66.967 33.63 67.27 35.700 71.400 36.33 72.67 37.34 74.67 28.50 57.00 29.00 58.00 29.50 59.00 33.33 66.65 30.00 60.00 30.50 61.00 31.25 62.50 32.05 64.105 32.50 65.00 33.00 66.00 33.48 66.95 34.50 69.00 35.50 71.00 36.50 73.00 37.50 75.00 38.25 76.50 39.00 78.00 39.75 79.50 40.50 81.00 41.25 82.50 42.00 84.00 42.75 85.50 43.50 87.00 44.25 88.50 45.00 90.00 IOAPIC 17.17 17.50 16.742 16.82 17.850 18.17 18.67 14.25 14.50 14.75 16.66 15.00 15.25 15.63 16.026 16.25 16.50 16.74 17.25 17.75 18.25 18.75 19.13 19.50 19.88 20.25 20.63 21.00 21.38 21.75 22.13 22.50
Block Diagram
PLL2 /2 X1 X2 XTAL OSC PLL1 Spread Spectrum 48MHz 24_48MHz
REF (1:0)
CPU DIVDER
CPUCLK (2:0) /2 CPU/2
SEL24_48# FREQ_APIC SDATA SCLK FS (4:0) PD# Control Logic Config. Reg.
IOAPIC DIVDER
IOAPIC (2:0)
PCI DIVDER
PCICLK (9:0) PCICLK_F
3V66 DIVDER
3V66 (2:0)
9248-134 Rev A 8/22/00
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
ICS9248-134
ICS9248-134
General Description
The ICS9248-134 is a main clock synthesizer chip for Pentium II based systems using Rambus Interface DRAMs. This chip provides all the clocks required for such a system when used with a Direct Rambus Clock Generator(DRCG) chip such as the ICS9212-01. Spread Spectrum may be enabled by driving the SPREAD# pin active. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-134 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. The CPU/2 clocks are inputs to the DRCG.
Pin Descriptions
Pin number Pin name 1, 7, 13, 19, 25, 31, G ND 36, 41, 45 2 REF0 REF1 3 SEL24_48 4, 10, 16, 23, V DD 28, 35 5 X1 6 X2 8 PCICLK_F FS0 PCICLK0 FS1 PCICLK1 FS2 PCICLK2 FS3 Type PWR OU T OU T IN PWR IN OU T OU T IN OU T IN OU T IN OU T IN OU T IN OU T OU T IN IN I/O OU T OU T OU T PWR OU T G round pins 14.318M Hz reference clock outputs at 3.3V 14.318M Hz reference clock outputs at 3.3V Logic input to select 24 or 48M Hz for pin 26 output Power pins 3.3V X TAL_IN 14.318M Hz crystal input X TAL_O UT Crystal output Free running PCI clock at 3.3V . Synchronous to CPU clocks. Not affected by the PCI_STOP# input. Logic - input for frequency selection PCI clock output at 3.3V . Synchronous to CPU clocks. Logic - input for frequency selection PCI clock output at 3.3V . Synchronous to CPU clocks. Logic - input for frequency selection PCI clock output at 3.3V . Synchronous to CPU clocks. Logic - input for frequency selection PCI clock outputs at 3.3V. Synchronous to CPU clocks. This asynchronous input powers down the chip when drive active(Low). The internal PLLs are disabled and all the output clocks are held at a Low state. 24 or 48M Hz output selectable by SEL24_48# (0=48M Hz 1=24M Hz) Fixed 48M Hz clock output. 3.3V Logic - input for frequency selection Clock input of I C input D ata pin for I C circuitry 5V tolerant 3.3V clock outputs. These outputs are stopped when CPU_STOP# is driven active.. H ost bus clock output at 2.5V. 2.5V clock outputs at 1/2 CPU frequency. Power pins for the CPU, CPU/2 & IO APIC clocks. 2.5V IOAPIC clocks at 2.5V. Synchronous with CPU CLKs.
2 2
Description
9 11 12
14, 15, 17, 18, 20, PCICLK (9:3) 21, 22 24 26 27 29 30 32, 33, 34 37, 38, 40 42 39, 43, 48 44, 46, 47 PD # 24_48M Hz 48M Hz FS4 SCLK SD ATA 3V66 (2:0) CPUCLK (2:0) CPU/2 V DDL IOAPIC (2:0)
2
ICS9248-134
Serial Configuration Command Bitmap
Byte 0: Functionality and frequency select register (Default = 0)
Bit Bit 2 FS4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit 3 Bit 1 Bit 0 Bit 7 FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Bit 6 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Bit 5 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Description Bit 4 CPU FS0 0 103.00 1 105.00 0 100.45 1 100.90 0 107.10 1 109.00 0 112.00 1 114.00 0 116.00 1 118.00 0 133.30 1 120.00 0 122.00 1 125.00 0 128.21 1 130.00 0 132.00 1 133.90 0 138.00 1 142.00 0 146.00 1 150.00 0 153.00 1 156.00 0 159.00 1 162.00 0 165.00 1 168.00 0 171.00 1 174.00 0 177.00 1 180.00 PWD CPU/2 51.50 52.50 50.225 50.45 53.550 54.50 56.00 57.00 58.00 59.00 66.65 60.00 61.00 62.50 64.105 65.00 66.00 66.95 69.00 71.00 73.00 75.00 76.50 78.00 79.50 81.00 82.50 84.00 85.50 87.00 88.50 90.00 PCI 34.33 35.00 33.483 33.63 35.700 36.33 37.34 28.50 29.00 29.50 33.33 30.00 30.50 31.25 32.05 32.50 33.00 33.48 34.50 35.50 36.50 37.50 38.25 39.00 39.75 40.50 41.25 42.00 42.75 43.50 44.25 45.00 3V66 68.67 70.00 66.967 67.27 71.400 72.67 74.67 57.00 58.00 59.00 66.65 60.00 61.00 62.50 64.105 65.00 66.00 66.95 69.00 71.00 73.00 75.00 76.50 78.00 79.50 81.00 82.50 84.00 85.50 87.00 88.50 90.00 IOAPIC 17.17 17.50 16.742 16.82 17.850 18.17 18.67 14.25 14.50 14.75 16.66 15.00 15.25 15.63 16.026 16.25 16.50 16.74 17.25 17.75 18.25 18.75 19.13 19.50 19.88 20.25 20.63 21.00 21.38 21.75 22.13 22.50 0 1 0
Bit 2, 7:4
Reserved Note 1
0 - Frequency is selected by hardware select, latched inputs 1 - Frequency is selected by Bit 2, 7:4 0 - Spread Spectrum disabled 1 - Spread spectrum enabled 0 - Running 1 - Tristate all outputs
Note 1: Default at power-up will be latched logic inputs to define frequency, as displayed by Bit 1.
3
ICS9248-134
Byte 1: CPU, Active/Inactive Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 40 38 37 42 47 46 44 PWD 1 1 1 1 1 1 1 X Description CPUCLK 0 CPUCLK 1 CPUCLK 2 CPU/2 IOAPIC0 IOAPIC1 IOAPIC2 (Reserved)
Byte 2: PCI Active/Inactive Register (1 = enable, 0 = disable)
Bit Pin # PWD Description
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
18 17 15 14 12 11 9 8
1 1 1 1 1 1 1 1
PCICLK7 PCICLK6 PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK_F
Notes: 1. Inactive means outputs are held LOW and are disabled from switching.
Notes: 1. Inactive means outputs are held LOW and are disabled from switching.
Byte 3: 3V66 Active/Inactive Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 34 33 32 3 2 PWD 1 1 1 X 1 1 X X Description 3V66_0 3V66_1 3V66_2 FS1# REF1 REF0 FS3# FS2#
Byte 4: PCI Active/Inactive Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 26 27 22 21 20 PWD 1 1 X 1 1 1 1 X Description 24_48MHz 48MHz FS0# (Reserved) PCICLK10 PCICLK9 PCICLK8 FS4#
Notes: 1. Inactive means outputs are held LOW and are disabled from switching.
Notes: 1. Inactive means outputs are held LOW and are disabled from switching.
Byte 5: Active/Inactive Register (1= enable, 0 = disable)
Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Pin # PWD 1 1 1 1 1 1 1 1 Description R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e )
Byte6: Active/Inactive Register (1= enable, 0 = disable)
Bit Pin # PWD Description
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
-
0 0 0 0 0 1 1 0
R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d
(Note) (Note) (Note) (Note) (Note) (Note) (Note) (Note)
Notes: 1. Inactive means outputs are held LOW and are disabled from switching.
Note: Don't write into this register, writing into this register can cause malfunction
4
ICS9248-134
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . . . Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V GND -0.5 V to VDD +0.5 V 0C to +70C -65C to +150C 115C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70 C; VDD = 3.3 V +/-5%; VDDL = 2.5 V +/-5% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS Input High Voltage VIH Input Low Voltage VIL VIN = VDD Input High Current IIH Input Low Current IIL1 VIN = 0 V; Inputs with no pull-up resistors Input Low Current IIL2 VIN = 0 V; Inputs with pull-up resistors Operating IDD3.3OP100 CL = 0 pF; Select @ 100 MHz Supply Current IDD3.3OP133 CL = 0 pF; Select @ 133 MHz VDD = 3.3 V; Input frequency Fi Input Capacitance1 CIN Logic Inputs X1 & X2 pins CINX Transition Time1 Ttrans To 1st crossing of target Freq. 1 Settling Time Ts From 1st crossing to 1% target Freq. Clk Stabilization1 TSTAB From VDD = 3.3 V to 1% target Freq.
1
MIN 2 VSS-0.3 -5 -200
11 27
MAX UNITS VDD+0.3 V 0.8 V A 0.1 5 A 2.0 A -100 71 160 mA 76 160 mA 14.318 16 MHz 5 pF 36 45 pF 3 ms 5 ms 3 ms
TYP
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70 C; VDD = 3.3 V +/-5%; VDDL = 2.5 V +/-5% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS Operating IDD2.5OP100 CL = 0 pF; Select @ 100 MHz Supply Current IDD2.5OP133 CL = 0 pF; Select @ 133 MHz Power Down IDD2.5PD CL = 0 pF; PWRDWN# = 0 Supply Current
1
MIN
TYP 15 18 272
MAX 75 90 400
UNITS mA mA A
Guaranteed by design, not 100% tested in production.
5
ICS9248-134
Group Offset
TA = 0 - 70 C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated) GROUP OFFSET MEASUREMENT LOADS MEASURE POINTS CPU to 3V66 0.0-1.5 ns; CPU leads. CPU @ 20pF, 3V66 @ 30pF CPU @ 1.25V, 3V66 @ 1.5V 3V66 to PCI 0.5-4.0 ns; 3V66 leads. 3V66 @ 30pF, PCI @ 30pF 3V66 @ 1.5V, PCI @ 1.5V CPU to IOAPIC 0.5-4.0 ns; CPU leads. CPU @ 20pF, IOAPIC @ 20pF CPU @ 1.25V, IOAPIC @ 1.25V CPU to PCI 0.5-4.0 ns; CPU leads. CPU @ 20pF, PCI @ 30pF CPU @ 1.25V, PCI @ 1.5V 1 Guaranteed by design, not 100% tested in production.
Electrical Characteristics - CPUCLK
TA = 0 - 70 C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN Output Impedance
1 1
TYP 30 32 2.24 0.31 -31 25 1.1 1.4 50 53 179 231
MAX UNITS 45 45 0.4 -19 1.6 1.8 55 175 275 350 V V mA mA ns ns % ps ps
RDSP2B RDSN2B VOH2B VOL2B IOH2B IOL2B tr2B tf2B dt2B tsk2B tjcyc-cyc2B
VO = VDD*(0.5) VO = VDD*(0.5) IOH = -12.0 mA IOL = 12.0 mA VOH = 1.7 V VOL = 0.7 V VOL = 0.4 V, VOH = 2.0 V VOH = 2.0 V, VOL = 0.4 V VT = 1.25 V; CPU frequencies < 135 MHz VT = 1.25 V VT = 1.25 V; CPU frequencies <135 MHz VT = 1.25 V; CPU frequencies >=135 MHz
13.5 13.5 2
Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time1 Fall Time1 Duty Cycle1 Skew1 Jitter, Cycle-to-cycle1
1
19
45
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - CPU/2
TA = 0 - 70 C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN Output Impedance1 Output Impedance1 Output High Voltage Output Low Voltage Output High Current Output Low Current 1 Rise Time 1 Fall Time 1 Duty Cycle Jitter, Cycle-to-cycle
1 1
TYP 30 31 2.2 0.31 -31 26 1.1 1.1 49 227 306
MAX UNITS 45 45 0.4 -19 1.6 1.6 55 275 350 V V mA mA ns ns % ps
RDSP2B RDSN2B VOH2B VOL2B IOH2B IOL2B tr2B tf2B dt2B tjcyc-cyc2B
VO = VDD*(0.5) VO = VDD*(0.5) IOH = -12.0 mA IOL = 12.0 mA VOH = 1.7 V VOL = 0.7 V VOL = 0.4 V, VOH = 2.0 V VOH = 2.0 V, VOL = 0.4 V VT = 1.25 V VT = 1.25 V; CPU frequencies <135 MHz VT = 1.25 V; CPU frequencies >=135 MHz
13.5 13.5 2
19
45
Guaranteed by design, not 100% tested in production.
6
ICS9248-134
Electrical Characteristics - 3V66
TA = 0 - 70 C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 30 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN Output Impedance
1 1
TYP 24 23 3.1 0.17 -51 41 1.4 1.5
MAX UNITS 55 55 0.4 -22 2 2 55 250 500 V V mA mA ns ns % ps ps
RDSP1 RDSN1 VOH1 VOL1 IOH1 IOL1 tr1 tf1 dt1 tsk1 Tjcyc-cyc1
VO = VDD*(0.5) VO = VDD*(0.5) IOH = -11 mA IOL = 9.4 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
12 12 2.4
Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time
1 1 1 1
16
Duty Cycle
45
50 89 173
Skew Jitter, Cycle-to-cycle1
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCICLK
TA = 0 - 70 C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 30 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN Output Impedance1 Output Impedance1 Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time
1 1 1
TYP 24 23 3.1 0.16 -50 42 1.8 1.5
MAX UNITS 55 55 0.4 -22 2.5 2.5 55 350 250 600 500 V V mA mA ns ns % ps ps
RDSP1 RDSN1 VOH1 VOL1 IOH1 IOL1 tr1 tf1 dt1 tsk1 Tjcyc-cyc1
VO = VDD*(0.5) VO = VDD*(0.5) IOH = -11 mA IOL = 9.4 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V, PCICLK(F:7) VT = 1.5 V, PCICLK(8:10) VT = 1.5 V, PCICLK(F:10) VT = 1.5 V
12 12 2.4
16
Duty Cycle
45
Skew Window1 Jitter, Cycle-to-cycle1
1
50 260 211 466 280
Guaranteed by design, not 100% tested in production.
7
ICS9248-134
Electrical Characteristics - 48 MHz, 24_48 MHz
TA = 0 - 70C; VDD = 3.3 V +/-5%; VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN Output Impedance
1 1
TYP 47 44 2.62 0.3 -27 22 2.1 2.2
MAX UNITS 60 60 0.4 -22 4 4 55 500 V V mA mA ns ns % ps
RDSP5 RDSN5 VOH5 VOL5 IOH5 IOL5 tr5 tf5 dt5 Tjcyc-cyc5
VO = VDD*(0.5) VO = VDD*(0.5) IOH = -16 mA IOL = 9 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V
20 20 2.4
Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time
1 1 1
16
Duty Cycle Jitter, Cycle-to-cycle1
1
45
51 375
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - REF
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN
TYP 48 44 2.6 0.3 -26 22 2.1 2.2
MAX UNITS 60 60 0.4 -22 4 4 55 1000 V V mA mA ns ns % ps
Output Impedance
1 1
RDSP5 RDSN5 VOH5 VOL5 IOH5 IOL5 tr5 tf5 dt5 Tjcyc-cyc5
VO = VDD*(0.5) VO = VDD*(0.5) IOH = -16 mA IOL = 9 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V
20 20 2.4
Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time
1 1 1
16
Duty Cycle Jitter, Cycle-to-cycle1
1
45
53 839
Guaranteed by design, not 100% tested in production.
8
ICS9248-134
Electrical Characteristics - IOAPIC
TA = 0 - 70 C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN Output Impedance1 Output Impedance1 Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time
1 1 1
TYP 26 31 2.24 0.31 -31 26 1.6 1.6
MAX UNITS 45 45 0.4 -19 2 2 55 250 500 V V mA mA ns ns % ps ps
RDSP4B RDSN4B VOH4B VOL4B IOH4B IOL4B Tr4B Tf4B Dt4B tsk4B Tjcyc-cyc4B
VO = VDD*(0.5) VO = VDD*(0.5) IOH = -12.0 mA IOL = 12.0 mA VOH = 1.7 V VOL = 0.7 V VOL = 0.4 V, VOH = 2.0 V VOH = 2.0 V, VOL = 0.4 V VT = 1.25 V VT = 1.25 V VT = 1.25 V
13.5 13.5 2
19
Duty Cycle Skew 1 Jitter, Cycle-to-cycle1
1
45
49 139 245
Guaranteed by design, not 100% tested in production.
9
ICS9248-134
Power Management Features:
PD# 0 1 CPUCLK CPU/2 IOAPIC LOW ON LOW ON LOW ON 3V66 LOW ON PCI LOW ON PCI_F LOW ON REF. 48MHz LOW ON Osc OFF ON VCOs OFF ON
Note: 1. LOW means outputs held static LOW as per latency requirement next page. 2. On means active. 3. PD# pulled Low, impacts all outputs including REF and 48 MHz outputs.
Power Management Requirements:
Latency Signal Signal State 1 (normal operation) 0 (power down) No. of rising edges of PCICLK 3mS 2max.
PD#
Note: 1. Clock on/off latency is defined in the number of rising edges of free running PCICLKs between the clock disable goes low/ high to the first valid clock comes out of the device. 2. Power up latency is when PWR_DWN# goes inactive (high to when the first valid clocks are dirven from the device.
10
ICS9248-134
General I2C serial interface information
The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 ICS clock will acknowledge each byte one at a time. Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 5 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit
How to Write:
Controller (Host) Start Bit Address D2(H) Dummy Command Code ACK Dummy Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Stop Bit
ACK Stop Bit ACK Byte 5 ACK Byte 4 ACK Byte 3 ACK Byte 2 ACK Byte 1 ACK Byte 0
ICS (Slave/Receiver)
How to Read:
Controller (Host) Start Bit Address D3(H) ICS (Slave/Receiver)
ACK
ACK Byte Count
Notes:
1. 2. 3. 4. 5. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown.
6.
11
ICS9248-134
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock synthesizer. Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The power down latency should be as short as possible but conforming to the sequence requirements shown below. The REF and 48MHz clocks are expected to be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete.
Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device). 2. As shown, the outputs Stop Low on the next falling edge after PD# goes low. 3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part. 4. The shaded sections on the VCO and the Crystal signals indicate an active clock. 5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
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ICS9248-134
SY MBOL
In Millimeters COMMON DIMENSIONS MIN MA X 2.413 0.203 0.203 2.794 0.406 0.343
In Inches COMMON DIMENSIONS MIN MA X .095 .008 .008 .110 .016 .0135
A A1 b c D E E1 e h L N V A RIA TIONS N 28 34 48 56 64
0.127 0.254 SEE V A RIA TIONS 10.033 7.391 0.381 10.668 7.595 0.635
.005 .010 SEE V A RIA TIONS .395 .291 .015 .420 .299 .025
0.635 BA SIC 0.508 1.016 SEE V A RIA TIONS 0 8
0.025 BA SIC .020 .040 SEE V A RIA TIONS 0 8
D mm. MIN 9.398 11.303 15.748 18.288 20.828 MA X 9.652 11.557 16.002 18.542 21.082 MIN .370 .445 .620 .720 .820
D (inch) MA X .380 .455 .630 .730 .830
6/1/00 R E VB
J EDE C MO- 118 DOC# 10- 0034
Ordering Information ICS9248yF-134-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
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ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

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